`timescale 1 ns / 10 ps // time-unit = 1 ns, precision = 10 ps module modMCounter_tb localparam M = 12, N = 4, period = 20 reg clk, reset wire complete_tick // desired_count is read from file // count is count provided by modMCounter.v wire count reg desired_count reg error_msg // message = error // = 4 bit data // = 12 rows in the file mod_m_counter_desired.txt reg read_data integer counter_data // for saving counter-data on file integer i = 0, j = 0, total_cycle = M // used for ending the simulation after M cycle // unit under test modMCounter #(. Line 10, where '1' is written // instead of 'a'. modMCounter_tb.v // note that the counter starts the count from 1 after reset (not from 0), // therefore file "mod_m_counter_desired.txt" starts with 1 (not from 0), // also one entry in the file is incorrect i.e. = read_data # 20 // write data to file using 'fdisplay' $fdisplay ( write_data, "%b_%b_%b_%b", a, b, sum_expected, carry_expected ) end $fclose ( write_data ) // close the file end endmodule a=0, b=1, sum_expected=0, carry_expected=0 for above line // but use of underscore makes the values more readable. adder_data.txt `timescale 1 ns / 10 ps // time-unit = 1 ns, precision = 10 ps module read_file_ex reg a, b // sum_expected, carry_expected are merged together for understanding reg sum_carry_expected // = 4 bit data // = 6 rows in the file adder_data.txt reg read_data integer i initial begin // readmemb = read the binary values from the file // other option is 'readmemh' for reading hex values // create Modelsim project to use relative path with respect to project directory $readmemb ( "input_output_files/adder_data.txt", read_data ) // or provide the compelete path as below // $readmemb("D:/Testbences/input_output_files/adder_data.txt", read_data) // total number of lines in adder_data.txt = 6 for ( i = 0 i < 6 i = i + 1 ) begin // 0_1_0_ are read in the same way, i.e.
#Modelsim altera not showing waveforms full
read_file_ex.v // note that, we need to create Modelsim project to run this file, // or provide full path to the input-file i.e. carry ( carry )) reg clk // note that sensitive list is omitted in always block // therefore always-block run forever // clock period = 2 ns always begin clk = 1 'b1 # 20 // high for 20 * timescale = 20 ns clk = 1 'b0 # 20 // low for 20 * timescale = 20 ns end always posedge clk ) begin // values for a and b a = 0 b = 0 # period // wait for period // display message if output not matched if ( sum != 0 || carry != 0 ) $display ( "test failed for input combination 00" ) a = 0 b = 1 # period // wait for period if ( sum != 1 || carry != 0 ) $display ( "test failed for input combination 01" ) a = 1 b = 0 # period // wait for period if ( sum != 1 || carry != 0 ) $display ( "test failed for input combination 10" ) a = 1 b = 1 # period // wait for period if ( sum != 0 || carry != 1 ) $display ( "test failed for input combination 11" ) a = 0 b = 1 # period // wait for period if ( sum != 1 || carry != 1 ) $display ( "test failed for input combination 01" ) $stop // end of simulation end endmodule half_adder_procedural_tb.v `timescale 1 ns / 10 ps // time-unit = 1 ns, precision = 10 ps module half_adder_procedural_tb reg a, b wire sum, carry // duration for each bit = 20 * timescale = 20 * 1 ns = 20ns localparam period = 20 half_adder UUT (.
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